Official pages

Please visit the official pages of this workshop hosted by the ETS organisers

LPonTR-2008:

http://www.cad.polito.it/~ets08/LPonTR/LPonTR.html

Lago Maggiore, Italy, May 29, 2008

LPonTR-2009:

http://www.imse.cnm.es/ets09/?act=workshop1

Seville, Spain, May 29, 2009

This workshop is held directly after the European Test Symposium

Aims

The International Workshop on Impact of Low Power Design on Test and Reliability (LPonTR) aims to bring together design, reliability and test engineers and researchers to discuss the impact of advanced low-power low-voltage design methodologies of nanometre silicon systems on test and reliability. Power and thermal issues, leakage, process variations, susceptibility to environmental and operation-induced interference are physical constraints that drive the development of low-power, process-tolerant design techniques. However, these techniques generate a new set of test and reliability challenges, questing for an innovative set of methodologies and tools.

Topics of Interest

The topics include, but not restricted to the following list:

• Power and process variations aware design and test
• Challenges of Ultra Low-power design on test and reliability
• Design for Variability at different abstraction levels and its effect on testing
• Reliability issues in silicon products on bellow 45 nm technologies
• Delay testing for high-performance low-power products
• Signal integrity in test mode
• Test and performance of physical on-chip infrastructures (power grid, clock distribution nets, etc.)
• Dynamic BIST and scan design for LP, process tolerant products
• Test and reliability issues in the presence of leakage
• Defect modelling, fault simulation and ATPG for emerging failure modes
• Discriminating physical defects from noise and uncertainty
• Low-power, low-voltage DfT
• Analog and mixed-signal low-power design, test and DfT
• test of SoC with power and thermal management (e.g., DVS, multi-V_th)
• Test and reliability of highly dependable, redundant systems
• Asynchronous design and test
• EDA tools to support LP, process-tolerant design
• Statistical and parametric test

Attraction of LPonTR

This workshop invites the authors to submit their work-in-progress in a form of a 2-page extended abstract. All submissions are reviewed by experts from industry and academia. The accepted papers are published in the workshop proceedings and their authors are invited to present their work as a talk, poster and/or a demonstration.

The workshop encourages feedback to the authors and networking (more than 8 companies and 15 universities were represented in 2008 – approx. 40 registrations). The aim of the feedback is to help the authors to finalise their work and to identify papers suitable for publication in a journal. Selected submissions are invitedfor publication as full papers in the Journal of Low Power Electronics (JOLPE). In 2008 seven papers were accepted to JOLPE after the second round of reviewing (Volume 4, Number 3, December 2008).

For companies this workshop gives an opportunity to expose themselves by giving a talk, participating in the panel discussion and/or demonstrating their tools/products in a dedicated session. Please see the past technical programme for more details.

Please visit the links below and download the proceedings of LPonTR’08. The technical programme of the past event shows how densely the workshop day was packed and indicates the overall value of the event.

LPonTR shares accommodation, catering and lunch facilities with the main ETS, which is known for its high standards. The registration to this workshop is separate from ETS. All communication including submission of manuscripts is normally done by email. The workshop chairs will be happy to answer all queries.

On-line Proceedings, Call for Papers and other documents

LPonTR’08

 

LPonTR’09

 

Chair / Co-Chair

Dr. Alex Bystrov(2008-2009), Newcastle University, Newcastle upon Tyne, U.K

Dr. Patrick Girard(2009) LIRMM, Montpellier, France

Prof. Joao Paulo Cacho Teixeira(2008), IST, Technical Univ. Lisbon (TUL), INESC-ID Lisboa, Portugal

Technical Programme Committee LPonTR’09 (updated 9th February 2009)

• Bashir Al-Hashimi, Univ. of Southampton, UK
• Karim Arabi, Qualcomm, USA
• Swarup Bhunia, Case Western Reserve Univ., USA
• Krish Chakrabarty, Duke Univ., USA
• Krishna Chakravadhanula, Cadence, USA
• Luigi Dilillo, LIRMM, France
• Dimitris Gizopoulos, Univ. of Piraeus, Greece
• Peter Harrod, ARM, UK
• Mokhtar Hirech, Synopsis, USA
• Gert Jervan, Tallinn Univ., Estonia
• Niraj Jha, Princeton University, USA
• Mark Kassab, Mentor Graphics, USA
• Sandip Kundu, Univ. Massachussets, USA
• Erik Larsson, Linkoping Univ., Sweden
• T.M. Mak, Intel, USA
• Hans Manhaeve, Q-Star, Belgium
• Nicola Nicolici, McMaster Univ., Canada
• Ilia Polian, Univ. Freiburg, Germany
• Irith Pomeranz, Purdue Univ., USA
• Srivaths Ravi, TI, India
• Juan Jose Rodriguez Andina, Univ. Vigo, Spain
• Mohammad Tehranipoor, Univ. Connecticut, US
• J. Paulo Teixeira, INESC-ID, Portugal
• Nur Touba, Univ. of Texas at Austin, USA
• Seongmoon Wang, NEC, USA
• Xiaoqing Wen, Kyushu Institute of Technology, Japan
• H.J. Wunderlich, Univ. of Stuttgart, Germany

LPonTR’08 contributors (inc. reviewers)

• Bashir Al-Hashimi, University of Southampton, UK
• David Atienza, Univ. of Madrid – Spain, EPFL – Switzerland
• Bernd Becker, Department of Computer Science University of Freiburg, Germany
• Paolo Bernardi, Politecnico di Torino, Italy
• Davide Bertozzi, Univ. of Ferrara, Italy
• Tobias Bjerregaard, Teklatech, Denmark
• Alberto Bosio, LIRMM – University of Montpellier, France
• Samir Boubezari, Atheros, Canada
• Alexander Bystrov, Newcastle University, UK
• Nick Cowern, Newcastle University, UK
• Giorgio Di Natale, LIRMM, France
• Luigi Dilillo, LIRMM / Univ. Montpellier II
• Stephan Eggersgluss, University of Bremen, Germany
• Santiago Fernandez-Gomez, Physical Design Manager, Apple Inc., USA
• Joan Figueras, University Barcelona, Spain
• Judit Freijedo, Universidad de Vigo – Departamento de Tecnologia Electronica, Spain
• Patrick Girard, LIRMM, Montpellier, France
• Elena Hammari, Norwegian University of Science and Technology, Norway
• Peter Harrod, ARM Ltd, UK
• Domenik Helms, OFFIS, Germany
• Richard Illman, Cadence, UK
• Michael Imhof, Institut fuer Technische Informatik Universitaet Stuttgart, Germany
• Michiko Inoue, Nara Institute of Science and Technology, Japan
• Gert Jervan, Tallinn University of Technology, Estonia
• Srinivas Katkoori, Department of Computer Science and Engineering, University of South Florida, Tampa
• Miyase Kohei, Kyushu Institute of Technology, Japan
• Rene Kothe, Brandenburg University of Technology Cottbus, Germany
• Sandip Kundu, University of Massachusetts, USA
• Wieslaw Kuzmicz, University of Warsaw
• Enrico Macii, Politecnico di Torino, Italy
• Grzegorz Mrugalski, Mentor Graphics Corp.
• Philipp Nenninger, ABB Corporate Research Centre, Germany
• Nicola Nicolici, McMaster University, Canada
• Michael O’Sullivan, Cadence, UK
• Satoshi Ohtake, Nara Institute of Science and Technology, Japan
• Irith Pomeranz, Purdue University, USA
• Janusz Rajski, Mentor Graphics Corporation, Poland
• Sudhakar Reddy, University of Iowa, USA
• Teresa Riesgo, Polytechnic University of Madrid, Spain
• Juan José Rodríguez-Andina, University of Vigo, Spain
• William Ruby, Sequence Design, Inc.
• Gordon Russell, Newcastle University, UK
• Sudip Roy, Department of Computer Science & Engineering, Indian Institute of Technology Kharagpur, India
• Scott Roy, University of Glasgow, UK
• Kewal Saluja, University of Wisconsin - Madison, USA
• Michihiro Shintani, Semiconductor Technology Academic Research Center, Japan
• Joao Paulo Teixeira, IST / TUL INESC-ID, Portugal
• Daniel Tille, University of Bremen, Germany
• Fabian Vargas, PUCRS, Brasil
• Xiaoqing Wen, Kyushu Institute of Technology, Japan
• T.W. Williams, Synopsys Inc., USA
• Mark Zwolinski, University of Southampton, UK

(Please let me know of any inaccuracies in this page A.Bystrov)

Revision: 9th February 2009