Department of Computing Science

University of Newcastle upon Tyne

"Behavioural REfinements for Asynchronous Circuit syntHesis" (BREACH)

funded by EPSRC (GR/M94359) £5.7K pounds.

GRANT REVIEW RESULT (06.03.2002) - Overall assessment: Tending to Outstanding
In particular

• Research Quality: Internationally leading (top)
• Cost Effectiveness: Outstanding (top)

This is a Visiting Fellowship for Dr. Nikolai Starodoubtsev, from Russian Academy of Science Institute of Analytical Instrumentation (St. Petersburg).

Two major objectives which would complement the achievements of the ASAP and ASTI projects (GR/J52327 and GR/L24038) and create a good background for its follow-up:

• (1) development of methods for better decomposition of asynchronous control circuits based on behavioural model refinement within the Petri net based synthesis environment;
• (2) investigation into the notion of speed-independence for modern self-timed implementation technologies;
• (3) development of more flexible technology mapping of asynchronous control circuits, satisfying both functional and non-functional requirements of the implementation libraries and design technologies.

Summary:

• (1) Work towards behavioural refinement techniques in the synthesis of asynchronous control circuits will be aimed at improving current techniques for logic decompoistion and technology mapping. The new methods will be based on manipulating circuit specifications at the state graph and Petri net levels, applying conditions imposed on the behavioural model by the requirements of a specific functional implementation, such as monotone (e.g. negative) gates.
• (2) Assessment of the delay-insensitivity and speed-independence criteria for modern practical design technologies, ranging from FPGAs, PLDs to submicrom custom VLSI design, will be made, to make important conclusions about wire delays, using of explicit inverters etc. and their effect on the synthesis algorithms.
• (3) Using the results of (1) and (3), new algorithms for logic decomposition and technology mapping tools will be developed and integrated with the existing software (e.g., Petrify).

Publications

N. Starodoubtsev, S. Bystrov, M. Goncharov, I. Klotchkov and A. Smirnov. Towards Synthesis of Monotonic Asynchronous Circuits from Signal Transition Graphs. Proceedings of the Second International Conference on Application of Concurrency to System Design (ACSD 2001) 27-29 June 2001, Newcastle upon Tyne, IEEE Comp. Society, 2001, pp. 179-188.

A. Smirnov, M. Goncharov, I. Klotchkov, and N. Starodoubtsev. A Technique to Automate STG Analysis and Refinement for CSC and Normalcy, Handouts of the First ACiD-WG Workshop (Framework 5), Neuchatel, Switzwerland, 12-13 February, 2001.

N. Starodoubtsev and A. Yakovlev. Isochronic Fork-Free Asynchronous Circuits, 9th Asynchornous UK Forum, Cambridge, Dec. 2000.

N. Starodoubtsev, A. Bystrov, and A. Yakovlev Semi-modular latch chains for asynchronous circuit design. Proc. 10th Int. Workshop on Power and Timing Modelling, Optimization and Simulation (PATMOS'2000), Goetingen, Germany, Sept. 2000, D. Soudris, P. Pirsch, E. Barke (Eds), LNCS 1918, Springer, pp. 168-177.

N. Starodoubtsev, M. Goncharov, I. Klotchkov and A. Smirnov. Synthesis of asynchronous interface circuits by STG refinement. In: A. Yakovlev and R. Nouta (Eds.) Proceedings of Int. Workshop on Asynchronous Interfaces: Tools, techniques, and Implementations (AINT'2000), TU Delft, The Netherlands, July 2000, ISBN 90-5326-037-4, pp. 65-74.

A.B. Smirnov, N. Starodoubtsev, I.V. Klotchkov and M. Goncharov, A technique to automate STG analysis and refinement for CSC and normalcy, Proc. Power and Timing Modeling, Optimization and Simulation (PATMOS), Yverdon-Les-Bains, Switzerland ,September 2001.

Further details about the project may be obtained from Alex Yakovlev, Dept. of Computing Science, University of Newcastle upon Tyne, NE1 7RU, tel. +44-191-2228184, email:

Alex.Yakovlev@ncl.ac.uk