School of Electrical, Electronic and Computer Engineering

University of Newcastle upon Tyne

"SeCuRE circuit dEsigN (SCREEN)

funded by EPSRC (GR/S81421) Ł526,124 pounds.
GRANT REVIEW RESULT (23/07/2008) - Overall assessment: Tending to Outstanding In particular:

Research Quality: Tending to Internationally leading
Research Planning and Practice: Internationally leading
Potential Scientific Impact: Internationally leading
Quality of Training and Experience: Outstanding
Communications of Research Output: Outstanding
Potential Benefits to Society: Tending to Outstanding
Cost Effectiveness: Tending to Outstanding

SCREEN Final Report and full publication list

Duration: 1.07.2004 - 30.06.2007
Principal Investigator: Prof. Alex Yakovlev
Co-investigators: Dr. Alexander Bystrov, Prof. David Kinniment, Dr. Albert Koelmans, Prof. Maciej Koutny
Research Staff: Dr Frank Burns, Mr Danil Sokolov
Project Partner: Atmel Corporation

The aim of this project is to develop a set of design methods and tools for enhancing the use of industrial EDA tools in the context of developing asynchronous hardware for secure systems. The enhanced design flow will, in the manner of contemporary synchronous flows, start from a hardware description language (such as VHDL or Verilog), where the functionality of a part will be described. After a sequence of steps through various tools, it will be able to produce a fabricatable form, i.e. the mask layout, of the specified circuit design. This flow will follow the traditional methodology for IC design, using mostly standard, existing industrial tools, enhanced only when needed by a small set of new tools, as described in the case for support. The key measure for success will be the ease with which an implementation with an improved (i.e. balanced) power signature can be generated for a complex digital design, minimising the need for the designer to learn asynchronous methods, because they will start from a "neutral" (i.e., not biased toward asynchronous implementation) initial specification. An additional measure of success will be the superiority of the demonstrator circuit(s), built using the new methods, with respect to a reference design, built with standard RTL techniques, in terms of the identified figures of merit (emitted EMI, security, area, etc. ). In this enhanced design flow, the system timing discipline will be considered along with other aspects affecting the circuit's security at the logic level, such as for example the use of value-masking codes and techniques for randomisation in the value and time domain. Therefore, depending on the requirements for the design, the new flow would not necessarily stipulate complete abandoning global clocking or any clocking for the entire system. In this way, our approach could be characterised as the best-effort synthesis of secure logic. The research will be undertaken in Newcastle University's Microelectronic Systems Design research group, in close collaboration with Atmel Smart Card ICs, a design and test facility at East Kilbride, specialising in high security microcontrollers. Atmel will provide this research project with important access to the industrial CAD flow and design examples for a case study chip, which will be aimed at demonstrating the impact of the self-timed logic design methods on security parameters of devices. On the design flow development, the researchers will interact with Universities of Cambridge, Manchester, Boston, Crete, Turin Polytechnic, and Cadence-Berkeley Research lab.

Progress by March 2005:
(1) Dual-rail logic with balanced switching activity
Dual-rail encoding, return to spacer protocols nad hazard-free logic can be used to resist power analysis attacks by making energy consumed per clock cycle independent of processed data. Standard dual-rail logic uses a protocol with a single spacer, e.g. all zeroes, which gives rise to energy balancing problems. We address this problems by incorporating two spacers; the spacers alternate between adjacent clock cycles. This guarantees all gates switch in every clock cycle regardless of the transmitted data values.
(2) Design tool Verimap and secure hardware design flow.
We have developed a design tool Verimap to generate dual-rail circuits automatically from the standard output (synchronous netlists) of the commerical synthesis tools. The tool also supports purely asynchronous design flow (synthesis of datapath) such as the one developed in the BESST project.
(3) Design benchmarks and case studies
We have produced a number of designs of cryptographic Those were developed in Cadence to the level of layout, simulated and compared with single-rail synchronous implementations to evaluate the method and the tool.
(4) Modelling security issues at abstract level: opacity
Recently, opacity has proved to be a promising technique for describing security properties. Much of the work has been couched in terms of Petri nets. In the ongoing work, we have extended the notion of opacity to the model of labelled transition systems and generalise opacity in order to better represent concepts from the work on information flow. In particular, we established links between opacity and the information flow concepts of anonymity and non-interference such as non-inference. We also investigated ways of verifying opacity when working with Petri nets.

More information to follow ...

Further details about the project may be obtained from Alex Yakovlev, School of EECE, University of Newcastle upon Tyne, NE1 7RU, tel. +44-191-2228184, email:

Alex.Yakovlev at ncl.ac.uk