Advanced Tutorial on Hardware Design and Petri Nets

Intended audience:

Researchers, PhD students working in the area of digital system design (looking for methods and tools to aid their design techniques), and those working with Petri nets and models of concurrency (looking for applications to their modelling, analysis, and synthesis methods).

Aims:

We aim at familiarising the audience with the basic ideas, techniques, and tools and developing practical skills in using Petri nets for modelling, analysing and synthesising digital systems, with the emphasis on asynchronous circuits.

Contents:

Hardware Modelling

Here we will consider methods for representing the behaviour of (predominantly asynchronous) hardware using Petri nets. The behaviour of circuits will be described at different levels of abstraction, ranging from high level models of processors down to the models of low level switching behaviour of logic circuits. Petri nets with suitable interpretation, such as Signal Transition Graphs (STGs) will be introduced. Problems with adequate capturing of hardware with analogue components, such as arbiters and circuits with hazards, as well as circuits with timing conditions will also be addressed.

Synthesis of Asynchronous Circuits

We will define the overall problem of synthesis of asynchronous circuits from their formal specifications based on interpreted Petri nets. The logic synthesis from STGs will be considered to a greater detail, covering steps involving the transformation of behavioural models at the STG and state graph levels. Some problems involved in efficient synthesis of large-scale asynchronous controllers will be discussed.

Automated Design Flow for Asynchronous Circuits

We will consider relationship between Petri nets and Hardware Description Languages, such as VHDL and Verilog, and describe an example of design flow for asynchronous circuits, which starts from a front end specification of the system described in behavioural Verilog. This specification is compiled into an interpmediate representation based on labelled Petri nets. The compilation process involves partitioning of the model into control and data paths and scheduling of the control flow. After that a number of tools are applied to synthesise logic implementation for control and data paths.

Additional topics

Time permitting we will also look at: