Dr. Alex Yakovlev
Dr. Albert Koelmans
asynchronous communications, computer system architecture, concurrent systems, embedded systems, real-time systems, synchronisation, verification, VLSI system design
The project addresses the development of a methodology and an associated set of software tools for the modelling, analysis and hardware implementation of fully asynchronous communication mechnisms (ACMs) for real-time embedded systems, where the notion of non-blocking communications is of prime importance. This methodology will provide the designer of such a system with methods to:
- specify ACMs, supporting the design of parallel systems with temporal "firewalls" between subsystems;
- validate the properties of data coherence and data freshness for ACMs;
- synthesise hardware for the implementation of ACMs;
- assess the effect of various physical parameters and properties, such as delays and metastability, on the functionality of ACMs.
The approach is aimed at achieving greater efficiency and productivity of ACM design compared to existing techniques. Rapid prototyping for hardware via VHDL/FPGA routes is envisaged.
This project will interact and exploit the results of two EPSRC-funded sister projects: HADES (on hazard-free arbiter design) and TIMBRE (on time predictable hardware platforms),
- Advancement in formal modelling and analysis of asynchronous communication mechanisms for real-time systems.
- Development of methods and software for synthesis and verification of hardware implementations for asynchronous communication mechanisms
- Development of methods for formal synthesis of multi-slot algorithms for asynchronous communication.
- A case study in a safety critical application of asynchronous communications.