Sponsor(s):
Sponsor(s):EPSRC
Contact Point:Prof. Alex Yakovlev
Dr. Albert Koelmans
Prof. Maciej Koutny
Prof. David Kinniment
Start Date:1.01.2000
Duration:36 months
Keywords:asynchronous circuits, concurrent systems, graphical interface, modelling, synthesis, visualisation, VLSI system design
Abstract:The project addresses the development of theoretical models and an associated set of algorithms and software tools for graphical representation and visualisation of highly complex asynchronous circuit behaviour. New tools will enable skilled designers to achieve greater quality and productivity, and greater confidence in their designs. For inexperienced designers, the tools will provide help, through adequate visual association, in understanding the complex character of concurrent processes in asynchronous circuits, and in capturing the various characteristic properties important for their synthesis. These tools will represent this behaviour, often measured in hundreds of thousands of reachable states in an appropriate, intuitively simple, form. These tools will be integrated with the existing software (e.g. Petrify ) for asynchronous circuit synthesis and analysis, experiments showing their effect on the productivity and quality of the design process will be performed. such as delays and metastability, on the functionality of ACMs.This project will interact and exploit the results of three EPSRC-funded projects: ASAP (on automated synthesis of asynchronous controllers), HADES (on hazard-free arbiter design) and COMFORT (on asynchronous communication mechanisms for real-time systems design)
Aims and Approach:
- Development of methods and algorithms for visualising state-transition systems and their properties with respect to circuit synthesis.
- Development of a formal model and method for representing branching concurrent processes and algorithms for visualising this model in "standard" circuit design forms, such as timing diagrams and state machine diagrams.
- Integration of the new software into tool Petrify and its design flow.
- Investigation of the new facilities on the quality of synthesised circuits and on the understandability of asynchronous circuit behaviour.
Further Information:
Design for Validation (DeVa)
Time-Predictable Hardware Platforms (TIMBRE)
Automated Synthesis of Asynchronous Control Circuits
Design of Reliable Asynchronous Controllers and Interfaces
Design tools for synthesis of asynchronous systems and circuits
Computing Science Research
j.b.hodgson@newcastle.ac.uk