funded by EPSRC (GR/S12036) £244,563 pounds.
GRANT REVIEW RESULT (23/10/2006) - Overall assessment: Tending to Outstanding In particular:
The project aims to develop an overall performance-oriented architecture and
design methodology for asynchronous, predominantly control, blocks which will
focus on the aspect of minimisation of input/output delay.
The project will provide a high-productivity design flow, based on circuit
compilation, with circuit structures, libraries, algorithms and tools for
synthesis, timing analysis and testing of self-timed circuits with low-latency.
Methods for incorporating generic scan based circuitry and on-line testing with
low speed penalty will be of particular interest.
The project will investigate a series of case studies and produce a
demonstrator VLSI circuit, e.g. a controller for on-chip communication,
to prove the feasibility of the design technology supporting both
productivity and performance.
An additional important outcome of the project will be its contribution to the
problems with resolving important tradeoffs in designing SoC as on-chip
networks, particularly: predictability and determinism versus average
performance, aggressiveness in speed versus testability and robustness.
STELLA Final Report
Further details about the project may be obtained from Alex Yakovlev, School of EECE, University of Newcastle upon Tyne, NE1 7RU, United Kingdom
email: Alex.Yakovlev at ncl.ac.uk