funded by EPSRC (EP/E044662/1) from 1st July 2007 for three years. Total amount of funding is 371,922 pounds.
The project focuses on the develpment of theory, architectures, models and circuit design techniques for functional blocks responsible
for processing events in a power efficient manner, to act as support logic to more general purpose computational blocks (IP cores)
placed in the environment which is inherently asynchronous and non-deterministic. The range of applications involves Real-time
Networks on Chip (RTNOCs), Wireless Sensor Networks and others.
Official webpage of STEP
The field of this research is the design, synthesis and verification of asynchronous and reactive event handling and processing hardware. This hardware is expected to work in an environment of concurrent, distributed, and real-time computation networks. These networks include both truly distributed systems such as wireless networking, sensor networks, and real-time networks as well as highly integrated on-chip networked computers with distributed processing. These systems are becoming more complex, and the traffic among the processing elements is increasing. Therefore handling the events which make up the traffic may determine much of the system performance and characteristics. Both asynchrony and non-determinism are inevitable for computation networks in the future, firstly because of the different timing requirements of different and diverse functional elements. Secondly, concurrent and distributed system implementations lead to greater asynchrony and non-determinism as semiconductor technology advances and the degree of integration increases (the International Technology Roadmap for Semiconductors (ITRS-05) "Design" document emphasizes multiple clock domains and source-synchronous signalling, and predicts networks of self-timed blocks). Existing methods of designing event-handling systems in hardware are rather ad hoc and have no systematic modelling and synthesis support. From this point of view, the project proposed here may have a major impact on the industrial as well as academic community. We aim to develop a design and synthesis method for self-timed hardware subsystems (called self-timed event processors or STEPs). STEPs will handle events arriving asynchronously and non-deterministically from multiple sources, and respond (such as by allocating resources, whose availability may also be asynchronously and non-deterministically changing) according to user specifications. Self-timing is in the sense that the triggering information is derived from the signals representing the events themselves, and STEPs may be used to form virtual self-timed reactive service blocks with off the shelf service IP cores such as processors or communications devices. We propose that this method will include a general STEP architecture, techniques for deriving wire delay aware designs for the integral parts of the architecture, and techniques for verifying such designs. A general mathematical modelling technique for STEPs at all levels of detail based on Petri nets will form the basis for the design/synthesis and verification work. We aim to develop the design and synthesis techniques to a degree where the process becomes systematic, highly algorithmic, and potentially automatic, and will cover all levels of detail down to hardware gate level schematics. It is our view that STEP technology will be a step forward in the event handling front, and will help towards the realization of systems of self-timed blocks envisioned in ITRS-05. The project will involve as a collaborator MBDA UK Ltd, a leading European privider of design technology for real-time distributed systems for missile control. The company has pioneered the Butler (awarded with The Queed's Award for Enterpise 2004) and Route-Table technologies, which provide stimulating starting ideas for STEP, such as tiled circuit architecture.
"Alex.Yakovlev" at "ncl.ac.uk"