Low Frequency Noise in 4H-SiC Lateral JFET Structures

Low frequency noise in 4H-SiC low-level signal-lateral JFETs was systematically investigated. In contrast to previous studies, which were based upon high power vertical structures, this work investigates the low-frequency noise behavior of low-level signal-lateral devices that are more relevant to the realization of small signal amplifiers. The JFETs studied share an identical cross section, but different gate lengths and widths. For high temperature operation between 300K and 700K at a gate source voltage (V_GS) of 0V, the normalized power spectral density (NPSD) of the JFETs is inversely proportional to frequency (f), referred to as 1/f noise. The NPSD increases monotonically up to a critical temperature, where it starts to decline. Two unique noise origins, fluctuations from bulk and SiO₂-SiC interface traps, were observed across all devices investigated. Low frequency noise for devices with a 50μm gate width is localized at the SiO₂–SiC interface, whereas for wider devices the noise is seen to be of bulk/substrate origin, following Hooge's model.