School of Electrical, Electronic and Computer Engineering

University of Newcastle upon Tyne

"Synchronizer Reliability in the Next Generation of SoC with Multiple Clocks" (SYRINGE)

funded by EPSRC (EP/C007298/1) from 1st July 2005 for three years. Total amount of funding is approx. 220,000 pounds.

The project focuses on the development of measurement techniques to validate synchronizer circuits at the reliability levels required, and the design of more robust circuits which will deliver the performance necessary for future multi-billion-transistor Systems on a Chip (SoC).

Official webpage of SYRINGE

Final Report on SYRINGE (November 2008)

The list of investigators:

David Kinniment (Emeritus Professor, acting as part-time Senior Research Associate on this project)
Gordon Russell
Alex Yakovlev (Principal Investigator)

Research Students:

Jun Zhou, Nikolaos Minas, Keith Heron

Industrial link:

Intel Corporation (Strategic Research Labs):
- Charles Dike

SYRINGE Project Summary:

As the size of systems on chip (SoC) has increased, it has become difficult or impossible to accurately distribute a single global clock across the entire system. Future systems are likely therefore to consist of many independently, or semi-independently clocked regions, with a need for synchronization of the data passing between them. Consequently there will be many more synchronizers whose performance and reliability is crucial to the performance of the system itself. Current synchronizers are untested at the levels of reliability required, and the increasing process fluctuations resulting from smaller dimensions are likely to worsen their relative performance. This three-year proposal aims to develop measurement techniques to validate synchronizer circuits at the reliability levels required, and to develop more robust circuits which will deliver the performance necessary for future multi-billion-transistor SoC.

Project Objectives

To develop synchronizer measurement techniques better suited to assuring reliability in SoC, in particular for characterising error rates beyond 20 .
To provide a firmer base for the theoretical prediction of reliability, including a better understanding of the role of noise in both conventional and unconventional synchronizer circuits.
To design more robust synchronizer circuits capable of good performance in nanometre technologies, with low supply voltages and large parameter fluctuations.

This project builds on the previous experience obtained in one of its predecessors: HADES
Further details about the project may be obtained from Alex Yakovlev, School of EECE, University of Newcastle upon Tyne, NE1 7RU, tel. +44-191-2228184, email:

"Alex.Yakovlev" at "ncl.ac.uk"