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School of Electrical, Electronic and Computer Engineering

University of Newcastle upon Tyne

"Next Generation of interconnection technology for multiprocessor SoC" (NEGUS)

funded by EPSRC (EP/C512812/1) from 1st March 2005 for three years. Total amount of funding is approx. 300,000 pounds.

NEGUS is part of a collaborative research project between School of EECE at Newcastle and School of Electronics and Computer Science at University of Southampton (EP/C512804/1). The project focuses on the development of scalable, reliableand energy-efficient interconnection technology needed for future multi-billion-transistor systems-on-chip (SoCs) designed using nanometer CMOS technology.

Official webpage of NEGUS

Final report on NEGUS (November 2008)

The list of investigators:

Research Associates:

Industrial link:

NEGUS Project Summary:

This project, which is collaboration between the School of Electronics and Computer Science at the University of Southampton and the Department of Electrical, Electronic and Computer Engineering at the University of Newcastle, focuses on the development of scalable, reliable and energy-efficient interconnection technology needed by future multi-billion-transistor system-on-chips (SoCs) designed using nanometer CMOS technology. This is a timely and necessary investigation if the microelectronics industry is to continue to produce SoCs for future application at affordable cost, as identified by the 2003 International Technology Roadmap for Semiconductors. Emphasis will be placed upon the employment of the emerging concept of Network-on-Chip (NoC) proposed to overcome complex on-chip communication problems, where SoC cores communicate with each other using packets through interconnection network, thus providing support for communication infrastructure re-use, reliable and power efficient interconnection technology.

For this research we will exploit expertise available at the collaborating universities that has recently produced efficient and low-power HW/SW co-design techniques that allow SoC designers to explore different system architectural designs (single/multi processors, hardware (ASIC and/or FPGA), asynchronous communication mechanisms (ACMs) and synchronization. The outcome of this research would be NoC based on-chip communication design methods, architectures, circuits and tools that are attractive for both industrial exploitation and further academic research. The research will be carried out in close collaboration with Prof P. Eles (Linkoping University, Sweden), Prof. L. Lavagno, Politecnico di Torino and MBDA UK.

This project builds on the previous experience obtained in its predecessors: COMFORT and COHERENT
Further details about the project may be obtained from Alex Yakovlev, School of EECE, University of Newcastle upon Tyne, NE1 7RU, tel. +44-191-2228184, email:

"Alex.Yakovlev" at ""