funded by EPSRC (EP/C007298/1) from 1st July 2005 for three years. Total amount of funding is approx. 220,000 pounds.
The project focuses on the development of
measurement techniques to validate synchronizer circuits at the reliability levels required, and
the design of more robust circuits which will deliver the performance necessary for future
multi-billion-transistor Systems on a Chip (SoC).
Official webpage of SYRINGE
Report on SYRINGE (November 2008)
As the size of systems on chip (SoC) has increased, it has become difficult or impossible to accurately distribute a single global clock across the entire system. Future systems are likely therefore to consist of many independently, or semi-independently clocked regions, with a need for synchronization of the data passing between them. Consequently there will be many more synchronizers whose performance and reliability is crucial to the performance of the system itself. Current synchronizers are untested at the levels of reliability required, and the increasing process fluctuations resulting from smaller dimensions are likely to worsen their relative performance. This three-year proposal aims to develop measurement techniques to validate synchronizer circuits at the reliability levels required, and to develop more robust circuits which will deliver the performance necessary for future multi-billion-transistor SoC.
"Alex.Yakovlev" at "ncl.ac.uk"