School of Engineering
(until August 2017 with School of Electrical and Electronic Engineering)
(in August 2002 moved from Department of Computing Science)
Newcastle University

Alex Yakovlev

Professor of Computing System Design

Asynchronous Research Group at Newcastle (async.org.uk)

Newcastle Async Group's Technical Report Series (async.org.uk/tr.html)

I am head of Microsystems Research Group

Research Interests

• Design of Asynchronous VLSI Systems
• Petri Nets and concurrency models in system design (Petri Net Home Page )
• Hardware Description Languages
• CAD Systems for VLSI
• Fault Tolerance and Reliability in VLSI
• Energy-driven and energy-modulated computing

My blog on Energy-Modulated computing link

Access to Workcraft tools

My scientific genealogy here

My PhD alumni (up to March 2024) here

Building a Common Vision for the UK Microelectronic Design Research Community

Publications

• Our first paper on Signal Graphs (known today as STGs):
  L. Ya. Rosenblum and A.V. Yakovlev.
  Signal graphs: from self-timed to timed ones,
  Proc. of the Int. Workshop on Timed Petri Nets,
  Torino, Italy, July 1985, IEEE Computer Society Press, NY, 1985, pp. 199-207.
  pdf
• An early attempt to promote self-timing and STGs in the completely synchronous world:
  A. Yakovlev.
  Designing Self-Timed Systems, VLSI SYSTEMS DESIGN,
  Vol. VI, No. 9, September 1985, pp. 70-90
  pdf
• A paper establishing interesting relationship between the interleaving and true causality semantics
  using algebraic lattices. It also identifies an connection between the classes of lattices and the property
  of generalisability of concurrency relations (from arity N to arity N+1),
  i.e. the conditions for answering the question such as,
  if three actions A, B and C are all pairwise concurrent, i.e. ||(A,B), ||(A,C), and ||(B,C), are they concurrent "in three", i.e. ||(A,B,C)?
  L. Rosenblum, A. Yakovlev, and V. Yakovlev.
  A look at concurrency semantics through "lattice glasses".
  In Bulletin of the EATCS (European Association for Theoretical Computer Science), volume 37, pages 175-180, 1989.
  pdf
• The first paper on VME bus controller design using STGs:
  A. Yakovlev and A. Petrov.
  Petri nets and parallel bus controller design.
  Proc. of 11th Int. Conf. on Applications and Theory of Petri Nets, Paris, France, June 1990
  pdf
  This paper also contains a first attempt to analyse Complete State Coding without building the reachability graph of an STG, using the-scalled coupledness relations (today known as lock relations)
• An early paper about process even knowledge modelling and analysis (based on partial orders), which aims to develop requirements for a software tool to manipulate knowledge captured in the form of Labelled Event Nets, for use in industrial expertise.
  A. V. Yakovlev and A.I. Petrov.
  A process event knowledge model for industrial expertise.
  Industrial Applications of Artificial Intelligence, J.L. Alty and L.I. Mikulich (Editors).
  Elsevier Science Publishers B.V. (North Holland), 1991, pp. 115-120
  pdf
• A technical report about analysing concurrent systems throughj lattices, written while I was at Polytechnic of Wales. This paper contains important results that connects causality and interleaving via a lattice-theoretic approach. It proves that the cumulative diagram of a persistent Petri net is a semi-modular lattice with a zero element, and that the cumulative diagram of a safe and persistent Petri net (or of a marked graph) is a distributive lattice with a zero element. These results hel;p to connect theory of semi-modular circuits by D.E. Muller with the classes of Petri nets.
  pdf
• An often sought-after paper (or, better say, my presentation slides) about designing arbiters with Petri nets:
  A. Yakovlev. Designing arbiters using Petri nets. Proceedings of the 1995 Israel Workshop on Asynchronous VLSI, Nof Genossar, Israel, March 1995, VLSI Systems Research Center, Technion, Haifa, Israel, pp. 178-201.
  pdf
• Papers about a fault-tolerant ring communication channel for an onboard control system. The system design was a precursor to today's Globally Asynchronous Locally Synchronous (GALS) systems as well as Networks-on-Chip (NOCs), because it was aimed to introduce asynchrony into the synchronous culture in an "evolutionary" way, re-using synchronous CPU cores, and replace the bus architectures, which were known for being poor in scaling and having proven to have lower reliability than the ring channel. The papers include three parts of the original publication in Avtomatika i Vychislitel'naya Tekhnika in 1988-89, translated and published by Allerton Press
  Part 1(Protocols)
  Part 2 (Adapter Implementation)
  Part 3 (Test and Recovery Methods)
  plus the paper which summarises this design and published in 1995: A. Yakovlev, V. Varshavsky, V. Marakhovsky and A. Semenov, Designing an asynchronous pipeline token ring interface, Proc. of 2nd Working Conference on Asynchronous Design Methodologies, London, May 1995, IEEE Comp. Society Press, N.Y., 1995, pp. 32-41. pdf)
  These papers contained original ideas about:
  - self-timed handshake communications and network interface to a synchronous CPU using FIFO,
  - use of m-of-n (Sperner) delay insensitive codes (we first used a 3-of-6 code to encode one half-byte and control tokens)
  - the channel switch routed packets in a broadcast mode with relative addressing
  - implementation method using Petri nets and direct mapping to control structures using David Cells
  - original channel acquisition protocol with arbitration using control tokens and identifiers
  - original self-synchronous methods for fault-detection, location and self-recovery (up to two faults in channel wires and adapters were allowed); a sliding redundancy self-repair method was used
  
• Paper about analysing concurrency semantics using relation-based approach. Similar techniques are now being developed in the domain of business process modelling and work-flow analysis: L.Ya. Rosenblum and A.V. Yakovlev. Analysing semantics of concurrent hardware specifications. Proc. Int. Conf. on Parallel Processing (ICPP89), Pennstate University Press, University Park, PA, July 1989, pp. 211-218, Vol.3. (pdf)
  
• Paper about synthesis of control circuits using STGs (called signal graphs). It formulates the formal conditions for implementability of STGs in logic circuits, particularly in the class of STGS that are marked graphs. It also shows, probably for the first time, a way to systematically synthesize a FIFO cell controller with two (fully decoupled) handshakes using STGs. In the process of synthesis the STG requires to be given two extra signals to resolve State Coding conflicts, using coupledness relations (originally developed in my PhD thesis of 1982) (pdf)
  
• Paper about the so called symbolic STGs, in which signals can have multiple values (which is often convenient for specifications of control at a more abstract level than dealing with binary signals) and hence in order to implement them in logic gates one needs to solve the problem of binary expansion or encoding, as well as resolve all the state coding issues on the way of synthesis of circuit implementation. (pdf)
  

Curriculum Vitae

Jobs and studentships in the Newcastle VLSI Design group

NEW Research Projects

Traces of Research Activity

I am Principal Investigator on EPSRC-funded projects:
RelCel , HOLISTIC , SURE , STEP , SEDATE (in collaboration with Universities of Manchester and Edinburgh - see main SEDATE website at Manchester), SYRINGE , NEGUS , SCREEN , STELLA , BESST , COHERENT , HADES, TIMBRE, COMFORT (see also COMFORT home page), MOVIE (see also MOVIE home page) ASTI (visiting fellowships of Prof. Alex Kondratyev and Prof. Luciano Lavagno), and BREACH (visiting fellowship of Dr. Nikolai Starodoubtsev from Russian Academy of Science, to work on Behavioural REfinements for Asynchronous Circuit syntHesis);
two British Council -funded joint projects, a Acciones Integradas (Part 2) project with Prof. Jordi Cortadella's group at Polytechnic University of Catalonia, Barcelona, Spain, and an ARC project with Prof. Monika Heiner's group at Brandenburg Technical University at Cottbus, Germany;
and participate in ESPRIT-funded projects DEVA and ACID-WG

(see also Asynchronous Research at Newcastle )

2010:

In the past:

1998:

I have organised Workshop on Hardware Design and Petri Nets within the 19th International Conference on Applications and Theory of Petri Nets Lisbon, Portugal, June 1998

I have co-organised a Special Interest Workshop on Exploitation of STG-based Design Technology (announcement and report) at St. Petersburg, Russia, 6-7 July 1998

Last ASTI project meeting (aka ACiD-WG special interest group meeting) with Luciano Lavagno and Alex Kondratyev has been held at Newcastle in the period of 20 Jul-5 Aug.

Our project ASAP (Automated Synthesis of Parallel and Asynchronous Controllers, EPSRC Research Grant GR/J52327) has been graded as follows:
Scientific or technical merit - alpha 5 (top)
Management and use of resources - Excellent (top)
ASAP publication list

Our long (and long-awaited!) overview paper in the recent Advanced Course on Petri nets :

A.V. Yakovlev and A.M. Koelmans
Petri nets and Digital Hardware Design
Lectures on Petri Nets II: Applications
Advances in Petri Nets, Lecture Notes in Computer Science, vol. 1492.
Springer-Verlag, 1998, pp. 154-236.

1999:

I have co-organised the Second Workshop on Hardware Design and Petri Nets within the 20th International Conference on Applications and Theory of Petri Nets Williamsburg, Virginia, USA, June 1999

I have co-organised the Third ACiD-WG Workshop , held on 18-19 January, 1999 in Newcastle.

I have served as a co-chair of the Programme Committee of ASYNC'99 to be held in Barcelona in April '99.

I have organised the Seventh Asynchronous UK Forum to be held in Newcastle, 20-21 December 1999

Our ASTI Project (Asynchronous circuit Synthesis and TestIng, EPSRC Research Grant GR/L24038,
visiting fellowships of Prof. Alex Kondratyev and Prof. Luciano Lavagno), has been graded as follows:
Scientific or technical merit - alpha 5 (top)
Management and use of resources - Excellent (top)

2000:

Our presentation at the ACiD-WG workshiop in Grenoble, January 2000 was about the perspectives of using direct translation techniques in synthesis of asynchronous controllers from Petri net specifications. Here are powerpoint and ps files

I have co-edited a book on Hardware Design and Petri Nets for Kluwer AP, based on the collection of papers presented at the HWPN workshops. The book has been published in March 2000. Hardware Design and Petri Nets (about the book)
Ordering the book from Kluwer AP

Our projects HADES (Hazard-free Arbiter DESign, EPSRC Research Grant GR/K70175)
and TIMBRE (TIMe-predicatBle hardwaRE platforms for real-time systems, EPSRC Research Grant GR/L28098)
have been respectively graded as follows:
HADES:
Scientific or technical merit - alpha 5 (top)
Management and use of resources - Excellent (top)
TIMBRE:
Scientific or technical merit - alpha 4
Management and use of resources - Excellent (top)

Our first silicon, the result of the HADES and COMFORT has been received from EUROPRACTICE on 9 June. The first photos are here

I have co-organised (with Jordi Cortadella and Luciano Lavagno) Advanced Tutorial on Hardware Design and Petri nets , held on 26 June, 2000 in Aarhus, Denmark within the 21st Int. Conf. On Appl. and Theory of Petri Nets (PN'2000)
The workshop materials are available from the PN2000 conference site:
Download: PDF (1.5 MB)
Download Addendum: PDF (724 Kb)

I have co-organised the AINT'2000 Workshop (Two-day workshop on Asynchronous Interfaces: Tools, Techniques, and Implementations) to be held in Delft, The Netherlands, 19-20 July 2000

My tutorial "Specifying Controllers using Petri Nets" at the 9th Async UK Forum was kindly given by Luciano Lavagno. The tutorial examples handout: gzipped postscript.

2001:

My talk "Communicating in Heterogeneously Timed Systems" (abstract) at the ICSA Colloquium in Edinburgh:
Slides in Powerpoint(1MB),
Handouts gzipped postscript(500KB)

I have co-organised (with Maciej Koutny, Albert Koelmans and Jason Steggles) a dual conference in Newcastle on 25-29 June 2001: 22nd Int. Conf. on Appl. and Theory of Petri nets and 2nd Int. Conf. on Appl. of Concurrency to System Design , and acted as a programme co-chair on the latter.

Papers presented at the 11th UK Async. Forum in Cambridge : tarred and gzipped

2002:

Tutorial "Logic Design of Asynchronous Circuits" by J.Cortadella, J. Garside and A. Yakovlev at ASPDAC/VLSI Design 2002 zipped (PPT and PS) files, including 'readme.txt'

Talk at the 2nd EC Framework 5 workshop in Munich (28 Jan 2002): "Behavioural synthesis of asynchronous controllers: a case study with a self-timed communication channel" (Powerpoint)

Monograph Logic Synthesis of Asynchronous Controllers and Interfaces by J. Cortadella, M. Kishinevsky, A. Kondrateyv, L. Lavagno and A. Yakovlev, has appeared from Springer in March 2002, ISBN3-540-43152-7.

Maciej Koutny and I have organised NATURAL COMPUTING DAYS AT NEWCASTLE on March 4-5, 2002.

Some publicity of our group's research (with certain technical inacurracies - bless the media!):
in TechExtreme ,
in Yahoo News ,
in Russian SciTechlibrary (and *almost* the same in Russian - please excuse someone's `wonderful' translation!),
in Suddeutche Zeitung
An article in Times Higher Education Supplement "Clock-free technology developed", THES, 26 April 2002 (p6) ( here )
Spiegel Online
KLIK Magazin
Perm' State University (in Russian)
British Trade (by Paul Shepherd)
Space Daily

My invited lecture "Is the Die Cast for the Token Game" (with contributions from Frank Burns, Alex Bystrov, Delong Shang and Danil Sokolov) was presented at 23rd Int. Conf. on Applications and Theory of Petri nets, Adelaide, Powerpoint slides
The full conference proceedings can be found here

The Petrify group has been selected as a finalist in the prestigeous Descartes Prize 2002 competition: Press Release
and Prize Catalogue
and Our diploma

Jordi Cortadella, Grzegorz Rozenberg and I edited the book "Advances in Petri Nets: Concurrency and Hardware Design", Springer, November 2002
The volume is also available online here

2003:

2004:

I gave an invited talk "Ten years of Petrifying" at the Fourth ACiD-WG Workshop in Turku, Finland, 28-29 June.

At this workshop I also gave a talk "Phase-difference based logic: principle and applications" , which introduced a new class of logic circuits, with the interesting property of "data-invariance" (the switching activity of the circuit is independent of the processed data), which may have useful applications in security, testing and quantum circuits (with decoherence).

I gave a talk Asynchronous Communication and Self-Timed Systems: Can they help simulate Brain? at the University Seminar "Brain-like Machines", Research Beehive, 11 Novewber 2004.

2005

My father Vladimir Yakovlev (Emeritus Professor of Control at the St. Petersburg Electrical Engineering University (also known as LETI)), Dr. Ivan Tyukin (graduate from LETI and research fellow at RIKEN Brain Science Institute, Japan)) and I visited Imperial College, EEE Department, in April 2004 on the invitation of Professor Peter Cheung. Here we are standing next to Denis Gabor .

I gave a talk Battling Complexity and Uncertainty via Asynchronous System Design at the UK Design Forum 2005, Manchester, 13-14 April 2005.

I gave an Advanced tutorial "Hardware Design and Petri nets" at the 26th International Conference On Application and Theory of Petri Nets and Other Models of Concurrency, Miami, USA, June 2005.

2006:

Ran Ginosar, Pol Marchal and I have organised the DATE'06 Friday Workshop "Future Interconnects and Networks on Chip", which took place under the auspices of DATE'06 in Munich. The details and presentations (talks and poster abstracts) are here

I served as a co-chair (with Jens Sparsoe) of the Programme Committee of ASYNC'06 held in Grenoble in March 2006.

Together with Maciej Koutny we visited Xidian University in Xi'an and Institute of Electronics of Chinese Academy of Sciences in Beijing with lectures on "Concurrency Models for Digital Systems Design" and "Some Aspects of Designing Systems on Chip". Some details are on the Xidian University website

I gave an invited talk "Coping with concurrency in hardware: teaching experiences" at the Workshop on Teaching Concurrency (TeaConc'06), held within ACSD'06 and ICATPN'06 in Turku, Finland, June 2006. ( talk abstract ).

Useful research links and docs

• Asynchronous Systems at Newcastle:
  • Asynchronous Research Group at Newcastle
  • "Async System Lab" (ASL) Seminars

Teaching Activities in 2007/08

• EEE1004 Project: C++ Programming (10 credit module, B.Eng. in E&E Eng, Stage 1)
  EEE1004 module description
  ( EEE1004 Course Assignments, Docs and Links)
  
• EEE8020 Design of VLSI Systems
  

TEMPUS/TACIS Activities:

Administrative Duties in 2001/02

• Degree Programme Director and Chairman of Board of Studies for:
  • BEng/MEng Microelectronics and Software Engineering
  • BEng/MEng/BSc Computer Systems Eng
• Departmental Induction/Registration Coordinator
• Allocation of Tutors/Tutees
• Admissions Computer Systems Eng/UCCA
• Member of Boards of Studies for CS and EEEng

Misc useful links

Mathematics and Theoretical CS:

American Mathematical Monthly

Topics in Mathematics

AMS (American Mathematical Society)

Math - General Resources

Theoretical CS database

SIGACT News Theory Calendar

The Hamiltonian Page

Planar Graphs

Eric's Treasure Trove of Mathematics

Interactive Mathematics Miscellany and Puzzles

Conway's "Life" Miscellany

Internet Resources for the College Math Student

Algorithms

Collected Algorithms of the ACM

The Stony Brook Algorithm Repository

Scott Gasch's Algorithm Archive

Geometry in Action: discrete and computational geometry

A Survey of Global Optimization Methods (Gray et al)

The Geometry Center

VLSI

EE Times Network

VLSIhoo

IBM Microelectronics

Yield and Reliability in VLSI

Great Microprocessors of the Past and Present

CPU Info Center

Research on Energy Aware Computing using Probabilistic Semiconductor Devices at Goergia Tech

Hardware Verification

Automated Theorem Proving (by Geoff Sutcliffe)

MATLAB:

MATLAB Tips and Previews

MATLAB at MathWorks

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E-mail

alex.yakovlev at ncl.ac.uk

Telephone numbers

Voice: +44-191-222-8184
Fax: +44-191-222-8180

Mailing address

School of EECE, Merz Court,
Newcastle University
Newcastle upon Tyne, NE1 7RU
United Kingdom

Geographical location

Room E4.13, Merz Court,
Newcastle University

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